1. Field of Invention
The present invention relates to an embedded capacitor for a substrate, and more particularly to an embedded capacitor with interdigitated structure for a substrate.
2. Related Art
Demands for high-density and high-speed performance have challenged current circuit board industry. In order to create more functionality in a smaller form factor, while supporting high clock speeds, with reduced EMI, at a reduced cost, design choices often involve compromising tradeoffs between size, cost and performance. Embedded passive elements enable designers to embed passive circuit elements inside the board, freeing up valuable real estate on the surface. The result is reducing board size and form factor, or additional functionality with the same board size. Embedded passive elements also provide increased placement and routing flexibility to put passive circuit elements in closer proximity to the I/O pads of an integrated circuit (IC). The shorter interconnects result in lower parasitic inductances, faster switching speeds and reduced noise in the circuit. Cost savings can be realized when the total value of the technology is taken into account, especially for applications with a high density of passive elements.
Metal-insulator-metal (MIM) capacitor is one of the common used embedded passive elements in a semiconductor substrate. A MIM capacitor is a particular type of capacitor having a dielectric sandwiched between two metal plates parallel to the circuit surface. The patterning of the top metal plate requires an additional process, and there will be alignment problems to underlying features (e.g., bottom metal plate) and vias to connect to interconnect layers. Another problem in fabricating MIM capacitor is a restriction in the selection of the dielectric materials. Due to potential interaction with or diffusion of the metals (such as copper) used for the metal plates, the dielectric material restriction may result in limited area capacitance.
Interdigitated capacitor is another embedded capacitor formed in a semiconductor substrate. Referring to FIG. 1, a conventional interdigitated capacitor in a substrate or in an integrated circuit is disclosed in U.S. Pat. No. 6,635,916. To provide a larger sidewall capacitance, the interdigitated capacitor includes at least two interdigitated patterns 101 connected through a plurality of vias 104 (marked with “x”). The vias 104 can be made into trenches that connect all along the length of some, most, or all of the metal lines, forming a wall of metal between lines that effectively extends through several levels. The interdigitated pattern 101 consists of a plurality of metal lines 102 alternatively connected to two different electrodes 106 and 108 in one layer of the substrate. The side-to-side capacitance is normally much larger than the layer-to-layer capacitance because the side-to-side distance is much smaller than the layer-to-layer distance in the integrated circuit. The interdigitated capacitor has a larger capacitance as the size shrinking of the IC process. However, the size shrinking also means a higher cost in manufacture; it is in a dilemma of reducing costs or enhancing the performance.
Applying the embedded capacitors to a laminated substrate, such as a package carrier or a printed circuit board, is another approach for the benefits of cost and performance. Referring to FIGS. 2a to 2c, an interdigitated capacitor 110 is disclosed. FIG. 2a shows a cross-sectional view of the interdigitated capacitor 110 along line A—A′ shown in FIG. 2b. The interdigitated capacitor 110 applied to a four-layer substrate consists of four patterns 111, 112, 113 and 114 disposed in different conductive layers and four via connecting structures. The first via connecting structure 205 has four via pads 211 and three connecting vias 207 between two different via pads 211. The second via connecting structure 206 has four via pads 212 and three connecting vias 208 between two via pads 212. Referring to FIG. 2b, the first pattern 111 consists of a plurality of first strips 231 parallel to each other, a plurality of second strips 232 interdigitated with the first strips 231, a first connecting line 221 connected with one end of each first strip 231, and a second connecting line 222 connected with one end of each second strip 232. The first via pads 211 is disposed in one corner around the first pattern 111. The third via pad 213 of another via connecting structure which is similar to the first via connecting structure 205 shown in FIG. 2a is disposed to an adjacent corner around the first pattern 111. The second via pad 212 is disposed on the diagonal corner with respect to the first via pad 211 and the fourth via pad 214 of the other via connecting structure similar to the second via connecting structure 206 is disposed on the right-down corner in FIG. 2b. However, because of the restrictions in the fabrication, the package carrier and a circuit board have via pads larger than the metal line. For example, the diameter of a via pad 211 at least is twice the width of the first connecting line 221. Please note that the space between the first via pad 211 and the fourth via pad 214 and the space between the second via pad 212 and the third via pad 213 are not used. In other words, it means a lower efficiency in layout, a larger circuit size and a higher cost.
Accordingly, it is desirable to provide an embedded capacitor with interdigitated structure for achieving high-capacitance and lower cost, especially for a substrate having large vias.